Ambric, Inc.

15655 SW Greystone Ct.

Suite 150

Beaverton, OR 97006



Area Code 503

601-6500 Voice

601-6596 Fax

 

Am2000 Family Massively Parallel Processor Array

Ambric introduced its teraOPS-class Am2000 family of massively parallel processor arrays (MPPAs) at In-Stat's Fall Microprocessor Forum in October, '06.

teraOPS-class Am2000 The only way to continue to deliver significantly higher levels of performance with power efficiency now and in the long run is by massive parallelism. Our solution to the architectural and programming challenges of massive parallelism clears the way to its practical adoption. The key to a practical solution for embedded computing was a relentless focus on the right programming model first; then Ambric invented new hardware architectures and circuit designs to enable this programming model.

The Am2000 family of MPPAs offers a profoundly easier development method compared to FPGAs hardware design methods or the nightmarish synchronization problems of programming multiple-DSPs. Ambric's Structural Object Programming Model (SOPM) is the key that unlocks engineering productivity and quality for high-performance embedded computing.

Please contact our sales department for more information.