Ambric's University Progam
The Ambric University Program was established to enable leading edge, massively parallel processing technology for computer science engineering research and course curricula. Massively parallel processing is recognized as the only way to keep scaling processor technology to keep up over time with Moore's Law. Universities that need to do research and educate engineers in massively parallel programming need a practical programming model, tools, boards, and reliable silicon with literally hundreds of different processors. Ambric's family of Am2000 MPPAs provides just that with its innovative globally-asynchronous interconnect fabric, a Kahn process network with bounded buffers. Ambric's MPPA technology uniquely enables massively parallel research that otherwise would be difficult or impossible to accomplish. Initial installations of the hardware and software tools started in July of 2007 and projects are now being implemented with the technology.
Benefits of membership in the Ambric University Program also include free or discounted access to Ambric's leading edge aDesigner™ massively-parallel software development tools, Am2045 MPPA developer's boards with 336 processors and 1.2 teraOPS and training.
The inability of general purpose processors to double their performance every eighteen months, as previously enabled by Moore's law, has created new opportunities for massively parallel processing devices, especially for high performance application domains. Reconfigurable architectures, such as Ambric's, represent a sweet-spot among FPGAs, ASICs, and DSPs, and may be the future of reconfigurable systems for streaming applications.
Some of the toughest problems in computing science involve the interaction of a digital system with the real world. Examples include speech recognition, computer vision, textual and image content recognition, robotic control, unmanned vehicles, sensor data collection, intelligent power management, and optical character recognition. These problems are extremely compute-intensive, but they are also massively parallel. My students and I are very excited to use Ambric's unique structural object programming model to see how some of these applications perform on this massively parallel computing platform.
A general principle in CERES' research is that functionality and performance are best achieved through the intelligent and massive cooperation among a large number of simple devices. For example, because of the downscaling following Moore's law, massive co-operation between processing elements can be utilized on the micro level. This makes it possible to implement extremely high performance, yet programmable, systems on a chip. The interconnections between the units at the chip, as well as at the board, level present challenging research questions. Consequently, Ambric's massively parallel chip, with its hundreds of processing elements, is an attractive silicon platform for embedded systems research.
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